The present invention relates to a semiconductor memory device. More particularly, it relates to a semiconductor memory device provided with a burn-in test function.
In the prior art, word lines and bit lines that are connected to a memory cell in a semiconductor memory device undergo a burn-in test. The burn-in test is performed during a final testing process, which is performed after a packaging process. Further, the burn-in test takes a long time since the word lines must be sequentially accessed. However, contemporary semiconductor memory devices are often delivered to a user's plant, which are still in the form of chips before undergoing the packaging process. Consequently, the burn-in test is normally performed during a wafer testing process.
In a memory device, such as a DRAM, word lines are selected one at a time in normal operation, during which information is read from or written to memory cells. Then, among the memory cells connected to the selected word lines, information is read from or written to the memory cell that is connected to a selected column.
When performing the burn-in test during the wafer testing process, multiple word lines and bit lines are simultaneously selected, and a stress voltage is applied between the word lines and bit lines or between the bit lines for a predetermined time to shorten the burn-in test time.
Accordingly, in addition to circuits for performing normal operations, a memory device having a burn-in test function must incorporate a circuit for performing the burn-in test. A large number of such burn-in test circuits has been proposed.
For example, Japanese Unexamined Patent Publication No. 10-340598 describes a switch circuit that provides a stress voltage to each bit line from an external device based on a test mode detection signal when performing the burn-in test. Japanese Unexamined Patent Publication No. 4-232693 also describes a switch circuit having a similar function.
These burn-in test circuits require a switch circuit for each bit line and a control signal line for each switch circuit. Thus, a burn-in circuit as described significantly increases the circuit area of the memory device.
Japanese Unexamined Patent Publication 11-86597 describes a test circuit that includes a switch circuit connected to each bit line to control the potential at the bit line. When performing the burn-in test, one of the switch circuits connected to a pair of the bit lines is activated to produce a potential difference between the pair of the bit lines. A sense amplifier is then activated to provide a stress voltage to each bit line.
The above burn-in test circuit also requires a switch circuit for each bit line and a control signal line for each switch circuit. Thus, this burn-in test circuit, too, significantly increases the circuit area of the memory device.
Japanese Unexamined Patent Publication 10-92197 describes a test circuit that activates a sense amplifier with a burn-in control signal. This causes the sense amplifier to provide a stress voltage to each bit line. Although a switch circuit is not required for each bit line in this burn-in test circuit, the operation of the sense amplifier makes it difficult to control the stress voltage provided to a pair of bit lines. In other words, the potential at each bit line when the sense amplifier is activated determines which one of the bit lines takes a high potential. Therefore, although short-circuits between a pair of bit lines are screened, short-circuits between bit lines of adjacent columns may not be screened. As a result, the burn-in test reduces the screening reliability.
Japanese Unexamined Patent Publication No. 6-223595 describes a test circuit that selects every write decoder and provides a stress voltage from a write amplifier to each bit line during a burn-in test.
Further, Japanese Unexamined Patent Publication No. 11-86597 describes a test circuit that provides a stress voltage from I/O circuits to the bit lines. Cell information is provided by the input and output through the I/O circuits, when the cell information is transferred between a data bus and columns.
The circuit area of cell arrays does not have to be increased in these test circuits since the decoders or I/O circuits, which are used during normal read and write operations, are employed to provide the stress voltage. During the burn-in test, however, every one of the bit lines applies a load to the write amplifier, which provides the stress voltage to the bit lines during the burn-in test. Thus, the load applied to the write amplifier is increased. This may cause an insufficient stress voltage being provided to the bit lines during the burn-in test and consequently decrease the screening reliability.
In addition, since all of the write decoders or I/O circuits are selected, the number of inputs of each decoder must increase, for example, from three to four. If the increase in the number of inputs occurs in many decoders, the number of logic gates will increase significantly. And the circuit area of peripheral circuits in a cell array will also increase.
As such, although many memory devices equipped with a burn-in test function have been proposed, the circuit area of cell arrays is increased when a switch circuit is connected to each bit line to ensure the supply of a stress voltage to each bit line.
Further, when a stress voltage is provided to each bit line without increasing the circuit area of cell arrays, the circuit area of peripheral circuits increases and each bit line does not acquire a sufficient stress voltage.